Current amplifier

ABSTRACT

A first transistor, a second transistor, a third transistor, and a fourth transistor, their source terminals being grounded, are provided. Further, a first feedback circuit connected between a gate terminal and a drain terminal in the first transistor, and having first impedance, a second feedback circuit connected between a gate terminal and a drain terminal in the second transistor, and having the first impedance, a current source for outputting a current, a first load circuit connected between the drain terminal of the first transistor and a first output terminal of the current source, and having second impedance, and a second load circuit connected between the drain terminal of the second transistor and a second output terminal of the current source, and having the second impedance are provided.

TECHNICAL FIELD

The present invention relates to a current amplifier.

BACKGROUND ART

In an amplifier used in, for example, a transceiver for moving object,high linearity is required.

In Nonpatent Literature 1 mentioned later, a current amplifier includinga first differential pair having two transistors, and a seconddifferential pair having two transistors is disclosed.

This current amplifier includes a first current source connected betweena source terminal of each of the two transistors that form the firstdifferential pair, and ground, and a second current source connectedbetween a source terminal of each of the two transistors that form thesecond differential pair, and the ground. The gain of this currentamplifier is proportional to the ratio of a current outputted from thefirst current source and a current outputted from the second currentsource.

Further, in this current amplifier, a feedback resister is connectedbetween the gate terminal and the drain terminal in each of the twotransistors that form the first differential pair.

In this current amplifier, because the feedback resisters are connected,distortion in the dynamic range of a gate-to-source voltage in the twotransistors that form the first differential pair is reduced. Namely,the distortion in the dynamic range of the gate-to-source voltage, thedistortion being caused by the first differential pair, is reduced.

Because, as a result of the reduction in the distortion in the dynamicrange, substantially the same voltage is applied to the firstdifferential pair and the second differential pair, so that thelinearity of the current amplifier is improved.

CITATION LIST Nonpatent Literature

Non Patent Literature 1: G. S. Sahota and C. J. Persico, “High dynamicrange variable-gain amplifier for CDMA wireless applications,” in Digestof Technical Papers—IEEE International Solid-State Circuits Conference,1997, vol. 40, pp. 374-375.

SUMMARY OF INVENTION Technical Problem

In the conventional current amplifier, because the second current sourceis connected between the source terminal of each of the two transistorsthat form the second differential pair, and the ground, a voltage occursbetween both terminals of the second current source. When a voltageoccurs between both the terminals of the second current source, due tothe influence of that voltage, the peak amplitude of a voltage at eachof the drain terminals of the two transistors that form the seconddifferential pair becomes small. When the peak amplitude of the voltageat each of the drain terminals becomes small, the linearity degrades,and the linearity further degrades with increase in the decrease amountof the peak amplitude.

Namely, the conventional current amplifier has a problem that eventhough the distortion in the dynamic range of the gate-to-source voltagein the two transistors that form the first differential pair is reducedby using the above-mentioned feedback resister, the linearity stilldegrades.

The present invention is made in order to solve the above-mentionedproblem, and it is therefore an object of the present invention toprovide a current amplifier that can eliminate the second current sourceconnected between the source terminal of each of the two transistorsthat forma second differential pair, and ground, thereby preventingdegradation in linearity.

Solution to Problem

A current amplifier according to the present invention includes: a firsttransistor whose source terminal is grounded and whose gate terminal isconfigured to receive a first signal; a second transistor whose sourceterminal is grounded and whose gate terminal is configured to receive asecond signal, the first signal and the second signal mutuallyconstituting a differential signal; a third transistor whose sourceterminal is grounded, whose drain terminal is connected to a firstoutput terminal, and whose gate terminal is configured to receive thefirst signal; a fourth transistor whose source terminal is grounded,whose drain terminal is connected to a second output terminal, and whosegate terminal is configured to receive the second signal; a firstfeedback circuit connected between the gate terminal and a drainterminal which are included in the first transistor, and having firstimpedance; a second feedback circuit connected between the gate terminaland a drain terminal which are included in the second transistor, andhaving the first impedance; a current source outputting a current; afirst load circuit connected between the drain terminal of the firsttransistor and an output terminal of the current source, and havingsecond impedance; and a second load circuit connected between the drainterminal of the second transistor and the output terminal of the currentsource, and having the second impedance.

Advantageous Effects of Invention

According to the present invention, because the configuration asdescribed above is provided, the second current source connected betweenthe source terminal of each of the two transistors that form a seconddifferential pair and ground is not required. As a result, there isprovided an effect of preventing degradation in linearity.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram showing a current amplifier according toEmbodiment 1 of the present invention;

FIG. 2 is an explanatory drawing showing an example in which an inputsignal source 8 is connected between an input terminal 1 a and an inputterminal 1 b in the current amplifier of FIG. 1;

FIG. 3 is a schematic diagram showing a current amplifier according toEmbodiment 2 of the present invention;

FIG. 4 is a schematic diagram showing a current amplifier according toEmbodiment 3 of the present invention;

FIG. 5 is an explanatory drawing showing a frequency response of thecurrent amplifier;

FIG. 6 is a schematic diagram showing a current amplifier according toEmbodiment 4 of the present invention;

FIG. 7 is an explanatory drawing showing a frequency response of acurrent amplifier;

FIG. 8 is a schematic diagram showing a current amplifier according toEmbodiment 6 of the present invention; and

FIG. 9 is an explanatory drawing showing a relation between a voltageamplitude V_(IN) of an input signal in an amplitude detector 23, and acurrent II.

DESCRIPTION OF EMBODIMENTS

Hereafter, for explaining the present invention in greater detail, someembodiments of the present invention will be described with reference tothe accompanying drawings.

Embodiment 1

FIG. 1 is a schematic diagram showing a current amplifier according toEmbodiment 1 of the present invention.

In FIG. 1, an input terminal 1 a is a terminal to which a first signalis inputted.

An input terminal 1 b is a terminal to which a second signal forming adifferential signal with the first signal is inputted.

In this Embodiment 1, an electric potential difference between the firstsignal inputted from the input terminal 1 a and the second signalinputted from the input terminal 1 b is referred to as an input voltageIN.

A first differential pair 2 includes a first transistor 2 a and a secondtransistor 2 b.

The first transistor 2 a and the second transistor 2 b are, for example,field effect transistors such as MOS (Metal Oxide Semiconductor)transistors.

A source terminal of the first transistor 2 a is grounded, and a gateterminal of the first transistor 2 a is connected to the input terminal1 a. The first signal is provided to the gate terminal of the firsttransistor 2 a.

A source terminal of the second transistor 2 b is grounded, and a gateterminal of the first transistor 2 b is connected to the input terminal1 b. The second signal is provided to the gate terminal of the secondtransistor 2 b.

A second differential pair 3 includes a third transistor 3 a and afourth transistor 3 b.

The third transistors 3 a and the fourth transistor 3 b are, forexample, field effect transistors such as MOS transistors.

A source terminal of the third transistor 3 a is grounded, a gateterminal of the third transistor 3 a is connected to the input terminal1 a, and a drain terminal of the third transistor 3 a is connected to afirst output terminal 7 a. The first signal is provided to the gateterminal of the third transistor 3 a.

A source terminal of the fourth transistor 3 b is grounded, a gateterminal of the fourth transistor 3 b is connected to the input terminal1 b, and a drain terminal of the fourth transistor 3 b is connected to asecond output terminal 7 b. The second signal is provided to the gateterminal of the fourth transistor 3 b.

A first feedback circuit 4 a is connected between the gate terminal anda drain terminal in the first transistor 2 a, and has first impedanceZ₁.

A second feedback circuit 4 b is connected between the gate terminal anda drain terminal in the second transistor 2 b. The second feedbackcircuit 4 b has the first impedance Z₁ as impedance being the samecharacteristics as the first impedance Z₁ that the first feedbackcircuit 4 a has.

Although it is assumed that the first feedback circuit 4 a and thesecond feedback circuit 4 b are implemented by, for example, resistors,as long as the feedback circuits have the first impedance Z₁, it doesnot matter what circuit configuration the feedback circuits have.

A current source 5 has an input terminal and an output terminal. Theinput terminal of the current source 5 is connected to a power sourceline having a voltage V_(dd).

A first load circuit 6 a is connected between the drain terminal of thefirst transistor 2 a and the output terminal of the current source 5,and has second impedance Z₂.

A second load circuit 6 b is connected between the drain terminal of thesecond transistor 2 b and the output terminal of the current source 5.The second load circuit 6 b has the second impedance Z₂ as impedancebeing the same characteristics as the second impedance Z₂ that the firstload circuit 6 a has.

Although it is assumed that the first load circuit 6 a and the secondload circuit 6 b are implemented by, for example, resistors, as long asthe load circuits have the second impedance Z₂, it does not matter whatcircuit configuration the load circuits have.

The first output terminal 7 a is a terminal from which the first signalamplified by the first transistor 2 a and the third transistor 3 a isoutputted.

The second output terminal 7 b is a terminal from which the secondsignal amplified by the second transistor 2 b and the fourth transistor3 b is outputted.

A capacitor 10 a is a capacitive component that blocks a DC componentincluded in the first signal inputted from the input terminal 1 a.

A capacitor 10 b is a capacitive component that blocks a DC componentincluded in the second signal inputted from the input terminal 1 b.

In this Embodiment 1, a current outputted from the first output terminal7 a and a current outputted from the second output terminal 7 b arereferred to as output currents I_(OUT).

Next, operations will be explained.

A bias is applied between the gate and the source of each of the firsttransistor 2 a and the second transistor 2 b that form the firstdifferential pair 2 by the current outputted from the current source 5.

The first signal inputted from the input terminal 1 a and whose DCcomponent is blocked by the capacitor 10 a is provided to the gateterminal of the first transistor 2 a. The second signal inputted fromthe input terminal 1 b and whose DC component is blocked by thecapacitor 10 b is provided to the gate terminal of the second transistor2 b.

Thus, at the drain terminal of the second transistor 2 a, a voltageamplitude corresponding to the first signal appears due to the secondimpedance Z₂ that the first load circuit 6 a has.

Further, at the drain terminal of the second transistor 2 b, a voltageamplitude corresponding to the second signal appears due to the secondimpedance Z₂ that the second load circuit 6 b has.

The voltage amplitude corresponding to the first signal is fed back tothe gate terminal of the first transistor 2 a by the first feedbackcircuit 4 a.

Further, the voltage amplitude corresponding to the second signal is fedback to the gate terminal of the second transistor 2 b by the secondfeedback circuit 4 b.

The linearity of the drain current of the first transistor 2 a withrespect to the first signal inputted from the input terminal 1 a isimproved through the feedback action of the voltage amplitudecorresponding to the first signal.

Further, the linearity of the drain current of the second transistor 2 bwith respect to the second signal inputted from the input terminal 1 bis improved through the feedback action of the voltage amplitudecorresponding to the second signal.

The drain current of the third transistor 3 a that forms the seconddifferential pair 3 is amplified in proportion to the transistor sizeratio of the third transistor 3 a and the first transistor 2 a.

Further, the drain current of the fourth transistor 3 b that forms thesecond differential pair 3 is amplified in proportion to the transistorsize ratio of the fourth transistor 3 b and the second transistor 2 b.

Conventionally, there exists a current amplifier in which the firstdifferential pair 2 is not disposed and a second differential pair 3 isconnected directly to the input terminals 1 a and 1 b. In the currentamplifier of this Embodiment 1, the linearity of the output currentsI_(OUT) with respect to the input voltage IN from the input terminals 1a and 1 b is improved in comparison with that of the conventionalcurrent amplifier.

FIG. 2 is an explanatory drawing showing an example in which an inputsignal source 8 is connected between the input terminal 1 a and theinput terminal 1 b shown in the current amplifier of FIG. 1.

In FIG. 2, V_(IN) denotes the voltage amplitude of the input signalsource 8 connected between the input terminal 1 a and the input terminal1 b, and R_(S) denotes the output impedance of the input signal source8. I_(OUT) denotes the current outputted from the first output terminal7 a and the second output terminal 7 b.

When the transconductance of each of the first and second transistors 2a and 2 b is denoted by g_(m1), the transconductance G_(m) in thecurrent amplifier of FIG. 2 is expressed as shown in the followingequation (1).

$\begin{matrix}{G_{m} = {\frac{I_{OUT}}{V_{IN}} = {\frac{- 1}{R_{S}} \times \frac{\frac{R_{S}Z_{1}}{R_{S} + Z_{1}} \times g_{m\; 1}}{1 + ( {\frac{Z_{1}Z_{2}}{Z_{1} + Z_{2}} \times g_{m\; 1} \times \frac{R_{S}}{R_{S} + Z_{1}}} )} \times \frac{I_{2}}{I_{1}}}}} & (1)\end{matrix}$

In equation (1), I₁ denotes a current flowing between the drain and thesource in each of the first and second transistors 2 a and 2 b, and I₂denotes a current flowing between the drain and the source in each ofthe third and fourth transistors 3 a and 3 b.

In equation (1), the transconductance g_(m1) in each of the first andsecond transistors 2 a and 2 b exhibits nonlinearity.

However, as shown in the following equation (2), when Z₁, Z₂, g_(m1) andR_(S) are set in such a way that the second term of the denominator inequation (1) becomes sufficiently larger than 1, g_(m1) in the numeratorof equation (1) and g_(m1) in the denominator of equation (1) can becanceled approximately. As a result, the transconductance G_(m) exhibitslinearity.

$\begin{matrix}{{{Second}\mspace{14mu} {Term}\mspace{14mu} {of}\mspace{14mu} {Denominator}\mspace{14mu} {in}\mspace{14mu} {Equation}\mspace{14mu} (1)} = {( {\frac{Z_{1}Z_{2}}{Z_{1} + Z_{2}} \times g_{m\; 1} \times \frac{R_{S}}{R_{S} + Z_{1}}} )1}} & (2)\end{matrix}$

As is clear from the above description, according to this Embodiment 1,the following components are included: a first transistor whose sourceterminal is grounded and whose gate terminal is configured to receive afirst signal; a second transistor whose source terminal is grounded andwhose gate terminal is configured to receive a second signal, the firstsignal and the second signal mutually constituting a differentialsignal; a third transistor whose source terminal is grounded, whosedrain terminal is connected to a first output terminal, and whose gateterminal is configured to receive the first signal; a fourth transistorwhose source terminal is grounded, whose drain terminal is connected toa second output terminal, and whose gate terminal is configured toreceive the second signal; a first feedback circuit 4 a connectedbetween the gate terminal and a drain terminal which are included in thefirst transistor 2 a, and having first impedance Z₁; a second feedbackcircuit 4 b connected between the gate terminal and a drain terminalwhich are included in the second transistor 2 b, and having the firstimpedance Z₁; a current source 5 outputting a current; a first loadcircuit 6 a connected between the drain terminal of the first transistor2 a and an output terminal of the current source 5, and having secondimpedance Z₂; and a second load circuit 6 b connected between the drainterminal of the second transistor 2 b and the output terminal of thecurrent source 5, and having the second impedance Z₂. As a result, asecond current source connected between the ground and each of thesource terminal of the third transistor 3 a and the source terminal ofthe fourth transistor 3 b is not required, and there is provided aneffect of being able to avoid degradation in the linearity.

Namely, according to this Embodiment 1, in each of the third and fourthtransistors 3 a and 3 b, the source terminal is grounded, and no currentsource is connected between the source terminal and the ground.Therefore, in the current amplifier of this Embodiment 1, the peakamplitude of the voltage of the drain terminal in each of the third andfourth transistors 3 a and 3 b does not become small due to theinfluence of a current source, and degradation in the linearity does notoccur, unlike in the case of the current amplifier described inNonpatent Literature 1. Therefore, the linearity can be improvedcomparing with than that of the current amplifier described in NonpatentLiterature 1.

Embodiment 2

In this Embodiment 2, a current amplifier that includes, as first andsecond load circuits, a differential inductor 9 having a center tapterminal 9 a will be explained.

FIG. 3 is a schematic diagram showing the current amplifier according toEmbodiment 2 of the present invention. In FIG. 3, because the samereference characters as those shown in FIG. 1 denote the same orcorresponding components, an explanation of the components will beomitted hereafter.

The differential inductor 9 has the center tap terminal 9 a.

The center tap terminal 9 a of the differential inductor 9 is connectedto an output terminal of a current source 5, a first input/outputterminal 9 b of the differential inductor 9 is connected to a drainterminal of a first transistor 2 a, and a second input/output terminal 9c of the differential inductor 9 is connected to a drain terminal of asecond transistor 2 b.

A part of the differential inductor 9 extending from the center tapterminal 9 a to the first input/output terminal 9 b has second impedanceZ₂, like the first load circuit 6 a of FIG. 1.

Further, a part of the differential inductor 9 extending from the centertap terminal 9 a to the second input/output terminal 9 c has the secondimpedance Z₂, like the second load circuit 6 b of FIG. 1.

Due to such a configuration, the differential inductor 9 operates in thesame way as the first load circuit 6 a and the second load circuit 6 bof FIG. 1.

In above-described Embodiment 1, in a case in which noise signals areinputted as in-phase signals from the input terminals 1 a and 1 b, avoltage corresponding to the in-phase signals occurs at a terminal inthe first load circuit 6 a, the terminal being on a side of the firsttransistor 2 a. Further, a voltage corresponding to the in-phase signalsoccurs at a terminal in the second load circuit 6 b, the terminal beingon a side of the second transistor 2 b. Therefore, amplified in-phasesignals are outputted from the first output terminal 7 a and the secondoutput terminal 7 b.

In this Embodiment 2, even in a case in which noise signals are inputtedas in-phase signals from the input terminals 1 a and 1 b, a voltagecorresponding to the in-phase signals does not occur at the firstinput/output terminal 9 b of the differential inductor 9. Further, inthe same case, a voltage corresponding to the in-phase signals does notoccur at the second input/output terminal 9 c of the differentialinductor 9. Therefore, the amplified in-phase signals can be preventedfrom being outputted from the first output terminal 7 a and the secondoutput terminal 7 b.

As is clear from the above description, according to this Embodiment 2,a differential inductor having a center tap terminal is used as thefirst load circuit and the second load circuit, the center tap terminalof the differential inductor is connected to the output terminal of thecurrent source, a first input/output terminal of the differentialinductor is connected to the drain terminal of the first transistor, anda second input/output terminal of the differential inductor is connectedto the drain terminal of the second transistor. Therefore, there isprovided an effect of being able to increase a common-mode rejectionratio (CMRR) comparing with that in above-described Embodiment 1, inaddition to the same effects as those provided by above-describedEmbodiment 1.

Embodiment 3

In this Embodiment 3, an example in which two current amplifiers eachhas the configuration shown in FIG. 1 or 3 are connected in parallelwill be explained.

FIG. 4 is a schematic diagram showing a current amplifier according toEmbodiment 3 of the present invention. In FIG. 4, the same referencecharacters as those shown in FIG. 1 denote the same or correspondingcomponents.

Although an example in which two current amplifiers each has aconfiguration shown in FIG. 1 are connected in parallel is shown in FIG.4, two current amplifiers each has a configuration shown in FIG. 3 maybe connected in parallel.

Each of the first and second amplifier circuits 11 and 12 corresponds tothe current amplifier shown in FIG. 1.

A first feedback circuit 4 a and a second feedback circuit 4 b in thefirst amplifier circuit 11 have the same role as the first feedbackcircuit 4 a and the second feedback circuit 4 b in the current amplifierof FIG. 1. To this end, the first feedback circuit 4 a and the secondfeedback circuit 4 b in the first amplifier circuit 11 have firstimpedance as impedance being the same characteristics, like the firstfeedback circuit 4 a and the second feedback circuit 4 b in the currentamplifier of FIG. 1.

Further, a first feedback circuit 4 a and a second feedback circuit 4 bin the second amplifier circuit 12 have the same role as the firstfeedback circuit 4 a and the second feedback circuit 4 b in the currentamplifier of FIG. 1. To this end, the first feedback circuit 4 a and thesecond feedback circuit 4 b in the second amplifier circuit 12 havefirst impedance as impedance being the same characteristics, like thefirst feedback circuit 4 a and the second feedback circuit 4 b in thecurrent amplifier of FIG. 1.

However, because the first amplifier circuit 11 and the second amplifiercircuit 12 have different characteristics, there is a difference betweenthe first impedance that the first feedback circuit 4 a and the secondfeedback circuit 4 b in the first amplifier circuit 11 have, and thefirst impedance that the first feedback circuit 4 a and the secondfeedback circuit 4 b in the second amplifier circuit 12 have.

In the example shown in FIG. 4, the first impedance that the firstfeedback circuit 4 a and the second feedback circuit 4 b in the firstamplifier circuit 11 have is Z_(1a), and the first impedance that thefirst feedback circuit 4 a and the second feedback circuit 4 b in thesecond amplifier circuit 12 have is Z_(1b).

A first load circuit 6 a and a second load circuit 6 b in the firstamplifier circuit 11 have the same role as the first load circuit 6 aand the second load circuit 6 b in the current amplifier of FIG. 1. Tothis end, the first load circuit 6 a and the second load circuit 6 b inthe first amplifier circuit 11 have second impedance as impedance beingthe same characteristics, like the first load circuit 6 a and the secondload circuit 6 b in the current amplifier of FIG. 1.

Further, a first load circuit 6 a and a second load circuit 6 b in thesecond amplifier circuit 12 have the same role as the first load circuit6 a and the second load circuit 6 b in the current amplifier of FIG. 1.To this end, the first load circuit 6 a and the second load circuit 6 bin the second amplifier circuit have second impedance as impedance beingthe same characteristics, like the first load circuit 6 a and the secondload circuit 6 b in the current amplifier of FIG. 1.

However, because the first amplifier circuit 11 and the second amplifiercircuit 12 have different characteristics, there is a difference betweenthe second impedance that the first load circuit 6 a and the second loadcircuit 6 b in the first amplifier circuit 11 have, and the secondimpedance that the first load circuit 6 a and the second load circuit 6b in the second amplifier circuit 12 have.

In the example shown in FIG. 4, the second impedance that the first loadcircuit 6 a and the second load circuit 6 b in the first amplifiercircuit 11 is Z_(2a), and the second impedance that the first loadcircuit 6 a and the second load circuit 6 b in the second amplifiercircuit 12 have is Z_(2b).

Next, operations will be explained.

A first signal is inputted from an input terminal 1 a in the firstamplifier circuit 11, and the same signal as the first signal isinputted from an input terminal 1 a in the second amplifier circuit 12.

Further, a second signal is inputted from an input terminal 1 b in thefirst amplifier circuit 11, and the same signal as the second signal isinputted from an input terminal 1 b in the second amplifier circuit 12.

Thus, the first signal amplified by the first amplifier circuit 11 andthe first signal amplified by the second amplifier circuit 12 aresynthesized, and the amplified first signal after synthesis is outputtedfrom a first output terminal 7 a.

Further, the second signal amplified by the first amplifier circuit 11and the second signal amplified by the second amplifier circuit 12 aresynthesized, and the amplified second signal after synthesis isoutputted from a second output terminal 7 b.

Here, FIG. 5 is an explanatory drawing showing a frequency response ofthe current amplifier.

In FIG. 5, a relation between the frequency and the transconductanceG_(m) in the current amplifier is shown as the frequency response of thecurrent amplifier.

In FIG. 5, a broken line shows a case of the current amplifier ofEmbodiment 1, and a solid line shows a case of the current amplifier ofEmbodiment 3.

In this Embodiment 3, there is a difference between the first impedancethat the first feedback circuit 4 a and the second feedback circuit 4 bin the first amplifier circuit 11 have, and the first impedance that thefirst feedback circuit 4 a and the second feedback circuit 4 b in thesecond amplifier circuit 12 have. Further, there is a difference betweenthe second impedance that the first load circuit 6 a and the second loadcircuit 6 b in the first amplifier circuit 11 have, and the secondimpedance that the first load circuit 6 a and the second load circuit 6b in the second amplifier circuit 12 have.

Therefore, there is a difference between the transconductance G_(m)corresponding to the frequency in the first amplifier circuit 11, andthe transconductance G_(m) corresponding to the frequency in the secondamplifier circuit 12.

Therefore, in the case of the current amplifier of this Embodiment 3, asshown in FIG. 5, a flat frequency response is acquired within a widerband than that in a case in which only one current amplifier is disposedlike in the case of above-described Embodiment 1.

Embodiment 4

In above-described Embodiment 3, the example in which each of the firstand second amplifier circuits 11 and 12 includes a current source 5outputting a fixed output current is shown.

In this Embodiment 4, an example in which each of first and secondamplifier circuits 11 and 12 includes a current source 21 outputting avariable current and a control circuit 22 controlling the currentoutputted from the current source 21 will be explained.

FIG. 6 is a schematic diagram showing a current amplifier according toEmbodiment 4 of the present invention. In FIG. 6, the same referencecharacters as those shown in FIG. 4 denote the same or correspondingcomponents.

Both the current source 21 included in the first amplifier circuit 11and the current source 21 included in the second amplifier circuit 12are variable current sources each having an input terminal and an outputterminal. An input terminal of the current source 21 included in thefirst amplifier circuit 11 is connected to a power source line having avoltage V_(dd) in the first amplifier circuit 11, and an output terminalof the current source 21 in the first amplifier circuit 11 is connectedto both an end of a first load circuit 6 a in the first amplifiercircuit 11 and an end of a second load circuit 6 b in the firstamplifier circuit 11. An input terminal of the current source 21included in the second amplifier circuit 12 is connected to a powersource line having a voltage V_(dd) in the first amplifier circuit 12,and an output terminal of the current source 21 in the second amplifiercircuit 12 is connected to both an end of a first load circuit 6 a inthe second amplifier circuit 12 and an end of a second load circuit 6 bin the second amplifier circuit 12.

The control circuit 22 controls the current outputted from the currentsource 21 included in the first amplifier circuit 11, and also controlsthe current outputted from the current source 21 included in the secondamplifier circuit 12.

FIG. 7 is an explanatory drawing showing a frequency response of thecurrent amplifier.

In FIG. 7, a relation between the frequency and the transconductanceG_(m) in the current amplifier is shown as the frequency response of thecurrent amplifier.

Next, operations will be explained.

When the control circuit 22 performs control in such a way that thecurrent outputted from the current source 21 included in the firstamplifier circuit 11 and the current outputted from the current source21 included in the second amplifier circuit 12 have the same value, thefrequency response of the current amplifier represents a curve as shownby A in FIG. 7.

When the control circuit 22 performs control in such a way that thecurrent outputted from the current source 21 included in the firstamplifier circuit 11 is greater than the current outputted from thecurrent source 21 s included in the second amplifier circuit 12, thefrequency response of the current amplifier represents a curve as shownby B in FIG. 7.

When the control circuit 22 performs control in such a way that thecurrent outputted from the current source 21 included in the firstamplifier circuit 11 is less than the current outputted from the currentsource 21 included in the second amplifier circuit 12, the frequencyresponse of the current amplifier becomes a curve as shown by C in FIG.7.

Therefore, by controlling the current outputted from the current source21 included in the first amplifier circuit 11 and the current outputtedfrom the current source 21 included in the second amplifier circuit 12by means of the control circuit 22, the frequency response of thecurrent amplifier can be adjusted.

Embodiment 5

Although in above-described Embodiments 1 to 4, an example in which thefirst transistor 2 a, the second transistor 2 b, the third transistor 3a, and the fourth transistor 3 b are field effect transistors is shown,the first through fourth transistors are not limited to field effecttransistors.

For example, the first transistor 2 a, the second transistor 2 b, thethird transistor 3 a, and the fourth transistor 3 b may be bipolartransistors.

In the case in which bipolar transistors are used as the firsttransistor 2 a, the second transistor 2 b, the third transistor 3 a, andthe fourth transistor 3 b, the base terminals of the bipolar transistorscorrespond to the gate terminals of the first through fourth transistorsshown in above-described Embodiments 1 to 4.

Further, the emitter terminals of the bipolar transistors correspond tothe source terminals of the first through fourth transistors shown inabove-described Embodiments 1 to 4, and the collector terminals of thebipolar transistors correspond to the drain terminals of the firstthrough fourth transistors shown in above-described Embodiments 1 to 4.

Also in the case in which bipolar transistors are used as the firstthrough fourth transistors, the same effects as those provided byabove-described Embodiments 1 to 4 can be achieved.

Embodiment 6

In above-described Embodiments 1 to 5, the example in which the currentamplifier includes a current source 5 is shown.

In this Embodiment 6, an example in which an amplitude detector 23 isincluded as a current source 5 will be explained.

FIG. 8 is a schematic diagram showing a current amplifier according toEmbodiment 6 of the present invention. In FIG. 8, the same referencecharacters as those shown in FIG. 1 denote the same or correspondingcomponents, so that an explanation of the components will be omittedhereafter.

The amplitude detector 23 is a current source that includes a square-lawdetector circuit 24, constant current sources 25 and 26, and a currentmirror circuit 27, and is a circuit that outputs a current (I₀+I_(d))that is the sum of a current directly proportional to the square valueof the voltage amplitude of an inputted signal, and a fixed current.

The square-law detector circuit 24 includes a transistor 24 a and atransistor 24 b, and outputs a current I_(b) directly proportional tothe square value of the voltage amplitude V_(IN) of the inputted signal.

Each of the transistors 24 a and 24 b is a field effect transistor suchas a MOS.

A source terminal of the transistor 24 a is grounded, and a signalhaving the voltage amplitude V_(IN) is provided to a gate terminal ofthe transistor 24 a.

A source terminal of the transistor 24 b is grounded, a drain terminalof the transistor 24 b is connected to a drain terminal of thetransistor 24 a, and a signal having the voltage amplitude V_(IN) isprovided to a gate terminal of the transistor 24 a.

The constant current source 25 outputs a current I_(a) that is a fixedcurrent.

The constant current source 25 has an input terminal and an outputterminal, the input terminal of the constant current source 25 isconnected to a power source line V_(dd), and the output terminal of theconstant current source 25 is connected to the drain terminal of thetransistor 24 a and the drain terminal of the transistor 24 b.

The constant current source 26 outputs a current I_(d) that is a fixedcurrent.

The constant current source 26 has an input terminal and an outputterminal, the input terminal of the constant current source 26 isconnected to the power source line V_(dd), and the output terminal ofthe constant current source 26 is connected to a drain terminal of aP-channel MOS transistor 27 b in the current mirror circuit 27, a firstload circuit 6 a, and a second load circuit 6 b.

The current mirror circuit 27 includes a P-channel MOS transistor 27 aand the P-channel MOS transistor 27 b, and outputs a current I₀ on thebasis of the current I_(b) outputted from the square-law detectorcircuit 24 and the current I_(a) outputted from the constant currentsource 25.

In the P-channel MOS transistor 27 a, a source terminal is connected tothe power source line V_(dd), and a drain terminal and a gate terminalare connected to the output terminal of the constant current source 25,the drain terminal of the transistor 24 a, and the drain terminal of thetransistor 24 b.

In the P-channel MOS transistor 27 b, a gate terminal is connected tothe gate terminal of the P-channel MOS transistor 27 a, a sourceterminal is connected to the power source line V_(dd), and the drainterminal is connected to the output terminal of the constant currentsource 26, the first load circuit 6 a, and the second load circuit 6 b.

A resistor 28 a has an end connected to a power source line V_(dc), andanother end connected to the gate terminal of the transistor 24 a.

A resistor 28 b has an end connected to the power source line V_(dc),and another end connected to the gate terminal of the transistor 24 b.

A capacitor 29 a has an end connected to an input terminal 1 a, andanother end connected to the gate terminal of the transistor 24 a.

A capacitor 29 b has an end connected to an input terminal 1 b, andanother end connected to the gate terminal of the transistor 24 b.

Next, operations will be explained.

Because components other than the amplitude detector 23 are the same asthose of above-described Embodiment 1, only an operation of theamplitude detector 23 will be explained hereafter.

Because an end of the resistor 28 a is connected to the power sourceline V_(dc), a signal having a voltage amplitude V_(IN) is provided tothe gate terminal of the transistor 24 a of the square-law detectorcircuit 24.

Further, because an end of the resistor 28 b is connected to the powersource line V_(dc), a signal having the voltage amplitude V_(IN) isprovided to the gate terminal of the transistor 24 b of the square-lawdetector circuit 24.

The voltage amplitude V_(IN) is a voltage that is a result obtained bysubtracting a voltage drop in the resistor 28 a or 28 b from the voltageof the power source line V_(dc).

When a signal having the voltage amplitude V_(IN) is provided to thegate terminal of each of the transistors 24 a and 24 a, the square-lawdetector circuit 24 outputs a current I_(b) directly proportional to thesquare value of the voltage amplitude V_(IN) of the inputted signal tothe current mirror circuit 27.

The current I_(b) is represented by the following equation (3).

I _(b) =I _(c) +K _(i) V _(IN) ²   (3)

In equation (3), I_(c) denotes a constant direct current included in thecurrent I_(b), and K_(i) denotes a constant of proportionality.

The current mirror circuit 27 outputs a current Io as represented in thefollowing equation (4) to the first load circuit 6 a and the second loadcircuit 6 b on the basis of the current I_(b) outputted from thesquare-law detector circuit 24 and the current I_(a) outputted from theconstant current source 25.

I ₀ =K ₂((I _(c) −I _(a))+K ₁ V _(IN) ²)   (4)

In equation (4), K₂ denotes a mirror ratio of the current mirror circuit27.

Then, a current that is the sum of the current I₀ outputted from thecurrent mirror circuit 27 and the current I_(d) outputted from theconstant current source 25 is outputted to the first load circuit 6 aand the second load circuit 6 b.

As a result, a current I₁ flowing between a drain and a source in eachof first and second transistors 2 a and 2 b is represented by thefollowing equation (5).

I ₁ =I ₀ +I _(d) =K ₂(I _(C) −I _(a))+I _(d) +K ₁ K ₂ V _(IN) ²   (5)

Hereafter, some effects of this Embodiment 6 will be explained.

In a region in which the voltage amplitude V_(IN) of the input signal issmall, the current I₀ outputted from the amplitude detector 23 is small,and the current I₁ flowing between the drain and the source in each ofthe first and second transistors 2 a and 2 b is also small.

For example, signals recently used for mobile communications and so onare ones on which multi-level modulation is performed, and there is atendency that their peak to average power ratios are large. In a case inwhich the current amplifier is used for such applications, the averagecurrent consumption can be reduced.

By adjusting the current I_(a), the current I_(d), and the mirror ratioK₂, the inclination of the current I₁ with respect to the voltageamplitude V_(IN) of the input signal can be changed, as shown in FIG. 9.

FIG. 9 is an explanatory drawing showing relations between the voltageamplitude V_(IN) of the input signal and the current I₁ in the amplitudedetector 23.

In an example of FIG. 9, characteristics expressed by a solid line andcharacteristics expressed by a broken line are represented as twocharacteristics that the inclination of the current I₁ with respect tothe voltage amplitude V_(IN) of the input signal differs.

It is to be understood that any combination of two or more of theabove-described embodiments can be made, various changes can be made inany component according to any one of the above-described embodiments,and any component according to any one of the above-describedembodiments can be omitted within the scope of the present invention.

INDUSTRIAL APPLICABILITY

The present invention is suitable for a current amplifier havingmultiple transistors.

REFERENCE SIGNS LIST

1 a, 1 b input terminal, 2 first differential pair, 2 a firsttransistor, 2 b second transistor, 3 second differential pair, 3 a thirdtransistor, 3 b fourth transistor, 4 a first feedback circuit, 4 bsecond feedback circuit, 5 current source, 6 a first load circuit, 6 bsecond load circuit, 7 a first output terminal, 7 b second outputterminal, 8 input signal source, 9 differential inductor, 9 a center tapterminal, 9 b first input/output terminal, 9 c second input/outputterminal, 10 a, 10 b capacitor, 11 first amplifier circuit, 12 secondamplifier circuit, 21 current source, 22 control circuit, 23 amplitudedetector, 24 square-law detector circuit, 24 a, 24 b transistor, 25, 26constant current source, 27 current mirror circuit, 27 a, 27 b P-channelMOS transistor, 28 a, 28 b resistor, and 29 a, 29 b capacitor.

1. A current amplifier comprising: a first transistor whose sourceterminal is grounded and whose gate terminal is configured to receive afirst signal; a second transistor whose source terminal is grounded andwhose gate terminal is configured to receive a second signal, the firstsignal and the second signal mutually constituting a differentialsignal; a third transistor whose source terminal is grounded, whosedrain terminal is connected to a first output terminal, and whose gateterminal is configured to receive the first signal; a fourth transistorwhose source terminal is grounded, whose drain terminal is connected toa second output terminal, and whose gate terminal is configured toreceive the second signal; a first feedback circuit connected betweenthe gate terminal and a drain terminal which are included in the firsttransistor, and having first impedance; a second feedback circuitconnected between the gate terminal and a drain terminal which areincluded in the second transistor, and having the first impedance; acurrent source outputting a current; a first load circuit connectedbetween the drain terminal of the first transistor and an outputterminal of the current source, and having second impedance; and asecond load circuit connected between the drain terminal of the secondtransistor and the output terminal of the current source, and having thesecond impedance, wherein a differential inductor having a center tapterminal is used as the first load circuit and the second load circuit,the center tap terminal of the differential inductor is connected to theoutput terminal of the current source, a first input/output terminal ofthe differential inductor is connected to the drain terminal of thefirst transistor, and a second input/output terminal of the differentialinductor is connected to the drain terminal of the second transistor. 2.(canceled)
 3. The current amplifier according to claim 1, wherein afirst amplifier circuit including the first through the fourthtransistors, the first and second feedback circuits, the current source,and the first and second load circuits, and a second amplifier circuitincluding the first through fourth transistors, the first and secondfeedback circuits, the current source, and the first and second loadcircuits that are different from those included in the first amplifiercircuit, are connected in parallel, and the first impedance that thefirst and second feedback circuits included in the first amplifiercircuit have differs from the first impedance that the first and secondfeedback circuits included in the second amplifier circuit have, and thesecond impedance that the first and second load circuits included in thefirst amplifier circuit have differs from the second impedance that thefirst and second load circuits included in the second amplifier circuithave.
 4. The current amplifier according to claim 3, further comprisinga control circuit controlling both the current outputted from thecurrent source included in the first amplifier circuit and the currentoutputted from the current source included in the second amplifiercircuit.
 5. The current amplifier according to claim 1, wherein each ofthe first through fourth transistors is a field effect transistor. 6.The current amplifier according to claim 1, wherein each of the firstthrough fourth transistors is a bipolar transistor, a base terminal ofthe bipolar transistor is the gate terminal, an emitter terminal of thebipolar transistor is the source terminal, and a collector terminal ofthe bipolar transistor is the drain terminal.
 7. The current amplifieraccording to claim 1, wherein the current source outputs the currentthat is a sum of a current directly proportional to a square value of avoltage amplitude of an inputted signal, and a fixed current.